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August 2004 rev 2.0 DDR 14-Bit Registered Buffer
ASM4SSTVF16857
LVCMOS level at a valid logic state since VREF may
Features
* Fully JEDEC JC40 - JC42.5 compliant for DDR1 applications to include: PC1600, PC2100, PC2700 & PC3200 ( > JEDEC defined DDR 400 @ 200MHz ) * * * * Low voltage operation; VDD: 2.3V - 2.7V. SSTL_2 Class II outputs. Differential clock inputs. Available in 48 pin TSSOP and TVSOP packages.
not be stable during power-up. To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESETB must be held at a logic low level during power-up. In the JEDEC defined Registered DDR DIMM
application, RESETB is specified to be asynchronous with respect to CLK/CLKB; therefore, no timing relationship can be guaranteed between the two
Product Description
The ASM4SSTVF16857 is a universal 14-bit register (D F/F based), designed for 2.3V to 2.7V VDD . The device supports SSTL_2 I/O levels, and is fully compliant with the JEDEC JC40, JC42.5 DDR I specifications covering PC1600, PC2100, PC2700, and PC3200 operational ranges. 14-bit refers to 2Q outputs for each D input - designed for use in Stacked Registers (stacked memory devices), Buffered DIMM applications. Data flow from D to Q is controlled by the differential clock (CLK/CLKB) along with a controlled reset (RESETB). The positive edge of CLK is used to trigger the data transfer, and CLKB is used to maintain sufficient noise margins, whereas the RESETB input is designed and intended for use at power-up. The ASM4SSTVF16857 supports a low power standby mode of operation. A logic low level at RESETB, assures that all internal registers and outputs (Q) are reset to a logic low state, and that all input receivers, data (D) buffers, and clock (CLK/CLKB) are switched off. Note that RESETB should be supported with a
signals. When entering a low-power standby mode, the register will be cleared and the outputs will be driven to a logic low level quickly relative to the time to disable the differential input receivers. This ensures there are no "glitches" on any output. However, when coming out of low power standby mode, the register will become active quickly relative to the time taken to enable the differential input receivers. When the data inputs are at a logic level low and the clock is stable during the lowto-high transition of RESETB until the input receivers are fully enabled, the design ensures that the outputs will remain at a logic low level.
Applications
* JEDEC and Non JEDEC DDR Memory Modules *Planar configurations *Supports PC1600 - PC2100 - PC2700 - PC3200 * * SSTL_2I/O Provides a complete support solution for JEDEC JC42.5 (JC45) DDR I RDIMMs' when used with the ASM5CVF857 Zero Delay Buffer.
Alliance Semiconductor 2575, Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
Notice: The information in this document is subject to change without notice.
August 2004 rev 2.0 Block Diagram
CLK CLKB 38 39 34 48 35 R CLK D1 Q1
ASM4SSTVF16857
ASM4SSTVF16857
RESETB D1 VREF
To 13 other channels
Pin Configurations
Q1 Q2 GND VDDQ Q3 Q4 Q5 GND VDDQ Q6 Q7 VDDQ GND Q8 Q9 VDDQ GND Q10 Q11 Q12 VDDQ GND Q13 Q14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
D1 D2 GND VDD D3 D4 D5 D6 D7 CLKB CLK VDD GND VREF RESETB D8 D9 D10 D11 D12 VDD GND D13 D14
48-pin TSSOP & TVSOP 6.10 mm body, 0.50 mm pitch - TSSOP 4.40mm body, 0.40mm pitch - TSSOP (TVSOP)
DDR 14-Bit Registered Buffer
ASM4SSTVF16857
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ASM4SSTVF16857
Pin Descriptions
Pin # 1, 2, 5, 6, 7, 10, 11, 14, 15, 18, 19, 20, 23, 24 3, 8, 13, 17, 22, 27, 36, 46 4, 9, 12, 16, 21 25, 26, 29, 30, 31, 32, 33, 40, 41, 42, 43, 44, 47, 48 38 39 28, 37, 45 34 35 Pin Name Q (14:1) GND VDDQ D(14:1) CLK CLKB VDD RESETB VREF Type O P P I I I P I I Description Data output. Ground to entire chip. Output supply voltage. Data input. Positive clock input. Negative clock input. Core supply voltage. Rest Active low. Input reference voltage.
Truth Table1
Inputs RESETB L H H H L or H L or H CLK X or floating CLKB X or floating D X or floating H L X Q Outputs Q L H L Q0
2
Note: 1. H=High signal level, L=Low signal level, = transition from low to high, = transition from high to low, X = don't care 2. Output level before the indicated steady state input conditions were established.
DDR 14-Bit Registered Buffer
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August 2004 rev 2.0 Absolute Maximum Ratings
Parameter Storage Temperature Supply Voltage Input Voltage
1
ASM4SSTVF16857
Min -65 -0.5 -0.5
Max +150 3.6 VDD + 0.5 VDD + 0.5 50 50 50 100 55
Unit C V V V mA mA mA mA C/W
Output Voltage
1,2
-0.5
Input Clamp Current Output Clamp Current Continuous Output Current VDD, VDDQ or GND current/pin Package Thermal Impedance3
Note: 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This current will flow only when the output is in the high state level V0 > VDDQ. 3. The package thermal impedance is calculated in accordance with JESD 51. These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device reliability.
DDR 14-Bit Registered Buffer
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August 2004 rev 2.0 Recommended Operating Conditions
Guaranteed by design. Not 100% tested in production. Parameter VDD Supply voltage PC1600, PC2100, PC2700 PC3200 PC1600, PC2100, PC2700 PC3200 VTT VI VIH(DC) VIH(AC) VIL(DC) VIL(AC) VIH VIL VICR VID VIX IOH IOl TA Termination voltage Input voltage DC input high voltage AC input high voltage DC input low voltage AC input low voltage Input high voltage level RESETB Input low voltage level Common mode input range Differential input voltage CLK CLKB 0.97 0.36 (VDDQ/2) - 0.2 1.7 Data Inputs Description Min 2.3 Typ 2.5
ASM4SSTVF16857
Max 2.7
Unit V
2.3
2.7 V
VDDQ
Output supply voltage
2.5
2.7
VREF
Reference voltage (VREF = VDDQ/2)
1.15
1.25
1.35 V
1.25 VREF - 0.04 0 VREF + 0.15 VREF + 0.31
1.3 VREF
1.35 VREF + 0.004 VDD V V V V VREF - 0.15 VREF - 0.31 V V V 0.7 1.53 V V V (VDDQ/2) +0.2 -20 20 V mA mA C
Cross-point voltage of differential clock pair High-level output current Low-level output current Operating free-air temperature
0
70
DDR 14-Bit Registered Buffer
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August 2004 rev 2.0 DC Electrical Characteristics - PC1600, PC2100, PC2700
TA = 0C to 70C, VDD = 2.5 0.2V, and VDDQ = 2.50.2V (unless otherwise stated) Guaranteed by design. Not 100% production tested. Symbol
VIK
ASM4SSTVF16857
Parameter
II = -18 mA
Test conditions
VDD
2.3 V 2.3 V to 2.7 V 2.3 V 2.3 V to 2.7 V 2.3 V 2.7 V
Min
Typ
Max
-1.2
Units
V V V
IOH = -100 A VOH IOH = -16 mA IOL = 100 A VOL IOL = 16 mA II All inputs Standby (static) IDD Operating (static) VI = VIH(AC) or VIL(AC) , RESETB = VDD RESETB = VDD, VI = VIH(AC) or VIL(AC) , CLK and CLKB switching 50% duty cycle RESETB = VDD, VI = VIH(AC) or VIL(AC), CLK and CLKB = switching 50% duty cycle; One data input switching at half clock frequency, 50% duty cycle IOH = -20 mA IO = 0 VI = VDD or GND
VDD - 0.2 1.95 0.2 0.35 5
V V A
RESETB = GND
2.7 V
0.01
A
2.7 V
25
mA
Dynamic operating (clock only) IDDD Dynamic operating (per each data input)
2.7 V
28
A/clock MHz
/clock 2.7 V 15 MHz/data input
rOH
Output high
2.3 V to 2.7 V
7
13.5
20
rOL
Output low |rOH - rOL|
IOL = 20 mA
2.3 V to 2.7 V
7
20
rO(D)
each separate bit Data inputs
IO = 20 mA, T A = 25 C
2.5 V
4
VI = VREF 310 mV, VICR = 1.25 V, VI(PP) = 360 mV
2.5 V 2.5 V
2.5 2.5 2.5
3.5 3.5 3.5
pF pF pF
Ci
CLK & CLKB RESETB VI = VDD or GND
2.5V
DDR 14-Bit Registered Buffer
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August 2004 rev 2.0 DC Electrical Characteristics -PC3200
TA = 0C to 70C, VDD = 2.6 0.2V, and VDDQ = 2.60.2V (unless otherwise stated) Guaranteed by design. Not 100% production tested.
ASM4SSTVF16857
Symbol
VIK
Parameters
Test conditions
II = -18 mA IOH = -100 A
VDD (V)
2.5 2.5 V to 2.7 2.5 2.5 V to 2.7 2.5 2.7
Min
Typ
Max
-1.2
Units
V V V
VDD - 0.2 1.95 0.2 0.35 5
VOH IOH = -8 mA IOL = 100 A VOL IOL = 8 mA II All inputs Standby (static) IDD Operating (static) VI = VIH(AC) or VIL(AC) , RESETB = VDD RESETB = VDD, VI = VIH(AC) or VIL(AC) , CLK and CLKB switching 50% duty cycle RESETB = VDD, Dynamic operating (per each data input) VI = VIH(AC) or VIL(AC) , CLK and CLKB = switching 50% duty cycle; One data input switching at half clock frequency, 50% duty cycle rOH rOL Output high Output low |rOH - rOL| each separate bit Data inputs Ci CLK & CLKB RESETB VI = VDD or GND IOH = -20 mA IOL = 20 mA 2.5 V to 2.7 2.5 V to 2.7 7 7 13.5 20 20 2.7 15 /clock MHz/data input IO = 0 2.7 328 A/clock MHz 2.7 25 mA VI = VDD or GND V A
V
RESETB = GND
2.7
0.01
A
Dynamic operating (clock only)
IDDD
rO(D)
IO = 20 mA, T A = 25 C
2.6
4
VI = VREF 310 mV, VICR = 1.25 V, VI(PP) = 360 mV
2.6 2.6 2.6
2.5 2.5 2.5
3.5 3.5 3.5
pF pF pF
DDR 14-Bit Registered Buffer
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August 2004 rev 2.0 Timing Requirements
(Over recommended operating free-air temperature range, unless otherwise noted). Guaranteed by design. Not 100% production tested.
* this parameter is not necessarily production tested.
ASM4SSTVF16857
VDDQ = 2.5V0.2V Symbol Parameters Min fCLOCK tW tACT* tINACT* Clock frequency Pulse duration, CK, CKLB high or low Differential inputs active time Differential inputs inactive time Setup time, fast slew rate tS Setup time, slow slew rate Hold time, fast slew rate th Hold time, slow slew rate Data after CLK, CLKB 0.9 1 4 Data before CLK, CLKB 0.9 0.75 0.75 2.5 22 22 Max 200
VDDQ = 2.6V0.1V Min Max 270 2.5 22 22 0.4 0.6 0.4 0.6 1 4
Unit
MHz ns ns ns ns ns
ns ns
tSL
Output slew rate, measurement point at 20% and 80%
V/ns
Note: 1. Data inputs must be low for a minimum time of tACT max, after which RESETB is taken high. 2. Data and clock inputs must be held at valid levels (not floating) for a minimum time of tINACTmax after which RESETB is taken low. 3. For data signal input slew rate >=V/ns 4. For data signal input slew rate >=0.5 V/ns and < 1V/ns 5. CLK,CLKB signals input slew rates are >=1V/ns
DDR 14-Bit Registered Buffer
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August 2004 rev 2.0 Switching Characteristics - PC1600, PC2100, PC2700
(Over recommended operating free-air temperature range unless otherwise noted.)
ASM4SSTVF16857
Symbol
From (input)
To (output)
VDD = 2.5 V 0.2 V Min Typ - Max - 2.8 - 5.0
Units
fmax tPD tphl CLK, CLKB RESETB Q Q
200 1.1 -
MHz ns ns
Switching Characteristics - PC3200
(Over recommended operating free-air temperature range unless otherwise noted.)
Symbol
From (input)
To (output)
VDD = 2.6 V 0.1 V Min Typ Max
Units
fmax tPD tphl CLK, CLKB RESETB Q Q
280 1.1 2.2 5.0
MHz ns ns
DDR 14-Bit Registered Buffer
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August 2004 rev 2.0 Parameter Measurement Information (VDD = 2.5 V 0.2V)
VTT RL = 50 From output under test Test point CL = 30 pF1 Load circuit
1
ASM4SSTVF16857
CL includes probe and jig capacitance.
Voltage and Current Waveforms
In the following waveforms, note that all input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Zo = 50 , input slew rate = 1 V/ns 20% (unless otherwise specified). The outputs are measured one at a time with one transition per measurement. VTT = VREF = VDDQ/2. VIH = VREF + 310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. VIL = VREF - 310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. tPLH and tPHL are the same as tpd. Input active and inactive times LVCMOS RESETB VDD 0V tinact 10%
1
Input
IDD
1
VDD/2
VDD /2 tact 90% or GND, and I O = 0 mA.
IDDH IDDL
IDD tested with clock and data inputs held at V
DD
Pulse duration
tw Input
Setup and hold times
VREF
VREF
VIH VIL
VI(pp) Timing input ts Input VREF VICR th VREF VIH VIL
Propagation delay times
DDR 14-Bit Registered Buffer
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August 2004 rev 2.0
VI(pp) Timing input VICR tPLH VTT VICR tPHL VTT
ASM4SSTVF16857
VOH VOL
Output
LVCMOS RESETB Input VDD/2 tPHL Output VTT
VIH VIL VOH VOL
DDR 14-Bit Registered Buffer
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August 2004 rev 2.0 Package Dimensions (48- Pin TSSOP)
ASM4SSTVF16857
N
c L E1 E
Symbol
Millimeters Min A A1 - 0.05 0.80 0.17 0.09 Max 1.20 0.15 1.05 0.27 0.20 Min -
Inches Max 0.047 0.006 0.041 0.011 0.008
0.002 0.32 0,007 0.0035
Index area 2 D A2 e b A1 A
Seating plane
A2 b c D E E1 e
See variations below 8.10 basic 6.00 6.20 0.319 basic 0.236 0.244
aaaC
0.50 basic 0.45 0.75
0.020 basic 0.018 0.030
6.10 mm (240 mil) body, 0.50 mm (0.020 mil) pitch TSSOP
L N a aaa
See variations below 0 - 8 0.10 0 - 8 0.004
Variations: D (mm) N Min 48 12.40 Max 12.60 Min 0.488 Max 0.496 D (inch)
DDR 14-Bit Registered Buffer
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August 2004 rev 2.0 Package Dimensions (Alternate size)
ASM4SSTVF16857
N
c L E1 E
Symbol
Millimeters Min A A1 - 0.05 0.80 0.13 0.09 Max 1.20 0.15 1.05 0.23 0.20 Min -
Inches Max 0.047 0.006 0.041 0.009 0.008
0.002 0.32 0,005 0.0035
Index area 2 D A2 e b A1 A
Seating plane
A2 b c D E E1 e
See variations below 6.40 basic 4.30 4.50 0.252 basic 0.169 0.177
aaaC
0.40 basic 0.45 0.75
0.016 basic 0.018 0.030
4.40 mm (173 mil) body, 0.40 mm (16 mil) pitch TVSOP
L N a aaa
See variations below 0 - 8 0.08 0 - 8 0.003
: Variations D (mm) N Min 48 9.60 Max 9.80 Min 0.378 Max 0.386 D (inch)
DDR 14-Bit Registered Buffer
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August 2004 rev 2.0
ASM4SSTVF16857
Ordering Codes
Quantity per reel
Ordering Number
Marking
Package Type
Temperature
ASM4SSTVF16857-48TT ASM4SSTVF16857-48TR ASM4SSTVF16857-48VT ASM4SSTVF16857-48VR
AS4SSTVF16857T AS4SSTVF16857T AS4SSTVF16857V AS4SSTVF16857V
48-pin TSSOP, tube 48-pin TSSOP, tape and reel 48-pin TVSOP, tube 48-pin TVSOP, tape and reel 2500 2500
0C to 70C 0C to 70C 0C to 70C 0C to 70C
DDR 14-Bit Registered Buffer
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ASM4SSTVF16857
Alliance Semiconductor Corporation 2595, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com
Copyright y Alliance Semiconductor All Rights Reserved Advance Information Part Number: ASM4SSTVF16857 Document Version: v2.0
(c) Copyright 2004 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
DDR 14-Bit Registered Buffer
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ASM4SSTVF16857
DDR 14-Bit Registered Buffer
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